Workshop on "Chip Design: From Logic to Layout"

Workshop on “Chip Design: From Logic to Layout”

Organized by the Department of Electronics and Communication Engineering (ECE)

📅 Date: 03.03.2026

🕘 Time: 9:00 AM

🎉 As part of RGF – Rathinam Grand Feast

The Department of Electronics and Communication Engineering (ECE) is proud to organize a one-day technical workshop on “Chip Design: From Logic to Layout” on 03rd March 2026 at 9:00 AM, as a part of the prestigious RGF – Rathinam Grand Feast.

This workshop is designed to provide participants with a comprehensive understanding of the complete VLSI chip design flow — starting from digital logic design concepts to physical layout implementation. The session will bridge the gap between theoretical foundations and real-world semiconductor design practices.

Participants will gain insights into:

• Fundamentals of digital logic and RTL design
• HDL-based modeling and simulation
• Synthesis and verification methodologies
• Physical design flow and layout considerations
• Industry-oriented tools and emerging trends in chip fabrication

The workshop aims to equip students with practical exposure to modern chip design techniques, enhancing their readiness for careers in VLSI, semiconductor industries, and core electronics domains.

Join us for this enriching technical experience and explore the journey of transforming logic into silicon!